The present invention relates to semiconductor device fabrication methods, and more particularly relates to planarization in semiconductor device fabrication process.
LOCOS (local oxidation of silicon) isolation techniques have been conventionally used to electrically isolate transistors. However, as transistors have been downsized drastically, the LOCOS isolation techniques have met with problems such as decrease in transistor regions due to bird's beaks and hence decrease in the breakdown voltage of transistors surrounded by isolations. In view of this, a technique for isolating devices using shallow trench isolations called STI has been developed as a new device isolation technique (for example, B. Davari et al., IEDM Tech. Digest, 92, (1988).)
In recent years, as the scale of integration of semiconductor devices has been increased, more and more devices and wiring have been downsized and multi-layered. Along with this, problems caused by roughness (step height) on substrate surfaces, which were not so much problematic in the past, have become noticeable. Such problems include, for example, size variation in resist masks formed by patterning of resists in a lithography process, and short circuits in wiring caused in step height portions. Step heights in a substrate surface, as well as, e.g., the performance of a semiconductor device fabrication system (such as an exposure system and an etching system), has a profound effect on size control in forming resist masks, wiring and the like. Therefore, a high degree of planarization of substrate surfaces has been strongly required in recent semiconductor fabrication processes.
In general, chemical mechanical polishing (CMP) is widely used to planarize substrate surfaces. A CMP process, which is used for device isolation, planarization of an insulating film between wires, formation of buried Cu wiring, and various other purposes, is indispensable in fabricating semiconductor devices.
In particular, step heights in a substrate surface due to STIs formed between MIS transistors greatly affect size control in forming gate electrodes of the MIS transistors. Thus, techniques for planarizing substrate surfaces with STIs formed therein have been developed actively for commercial use.
Hereinafter, a conventional technique for planarizing, using a CMP technique, a substrate surface, in which STIs are formed, will be described with reference to FIG. 9.
First, in a step shown in FIG. 9A, a silicon oxide film 2 and a silicon nitride film 3 are formed in sequence on a semiconductor substrate (a silicon substrate in this embodiment) 1. A resist 7 is then applied onto the silicon nitride film 3 and patterned by lithography, thereby forming openings 7a in the resist 7.
Next, in a step shown in FIG. 9B, with the resist 7 used as a mask, a dry-etching process is performed to remove the silicon nitride film 3, the silicon oxide film 2, and the silicon substrate 1 where they are located under the openings 7a, thereby forming trenches 4.
Subsequently, in a step shown in FIG. 9C, a silicon oxide film 5 is formed on the surfaces of the trenches 4, after which an insulating film 6 is formed to completely fill the trenches 4 and cover the silicon nitride film 3. In this step, a TEOS film or a silicon oxide film formed by a CVD process is used as the insulating film 6.
Then, in a step shown in FIG. 9D, the insulating film 6 is annealed and then polished by CMP until the silicon nitride film 3 is exposed. Finally, the silicon nitride film 3 is selectively removed by phosphoric acid, thereby forming STIs 8.
However, in any CMP systems, distribution of polishing rate (hereinafter referred to as polishing-rate distribution) of a target film being polished changes irregularly with time. Such changes with time in the target film's polishing-rate distribution produce in an STI formation process step for example, variations after polishing in the film thickness of a silicon nitride film that is a polishing stopper in CMP between where the silicon nitride film is in the central portion of the wafer and where it is in the peripheral portion thereof. As a result, variations occur in the step height of the device isolation region.
The variations in the step height of the substrate surface then cause variations in the size of gates formed later by lithography, for example. Consequently, semiconductor devices formed in the central and peripheral portions of the wafer might differ in characteristic.
As a method to solve such variations in the step height of a substrate surface resulting from variations in a film-thickness distribution in a wafer, a method is disclosed in Japanese Laid-Open Publication No. 2002-134466. In the method disclosed in the publication, part of a target film having large thickness in a wafer is subjected to a wet-etching process so that the target film is planarized to some extent, after which a planarization process by CMP is performed, thereby decreasing post-polishing variation in the step height of the wafer surface.